In a semiconductor device such as of a BGA (Ball Grid Array) type and a CSP (Chip Size Package) type, a die pattern smaller than the IC chip size and solder resist larger than the IC chip size and extending over the whole surface of a wiring board are formed on an IC chip adhesion side of the wiring board. A metallic pattern and solder resist having almost the same areas as in the IC chip adhesion side are formed on the side opposite to the IC chip adhesion side of the wiring board. A power-source pattern is formed on the perimeter of an IC chip, this power-source pattern and the IC chip are adhered with electroconductive adhesive, and the power-source pattern and the die pattern are connected with a wiring pattern (for example, refer to Patent Reference 1).
In a plastic package (semiconductor device), filling of a through hole is performed by filling up with conductive paste the inside of the through hole where a Cu plating layer which includes non-electrolyzed Cu plating and electrolysis Cu plating is formed on the surface of a wall. And a solder ball connection pad includes a part of a wiring pattern formed on the exposed surface of conductive paste and its perimeter, and Ni plating and Au plating are further performed on the solder ball connection pad (for example, refer to Patent Reference 2).
A molded member is fabricated by performing resin molding of a plurality of semiconductor chips collectively, in the state that the back surface of a strip substrate on which the semiconductor chips are mounted is vacuum-adsorbed to the lower die of a metal mold. Then, the strip substrate and molded member which are released from the metal mold are cut to obtain a plurality of semiconductor devices (for example, refer to Patent Reference 3).
[Patent Reference 1] Japanese Unexamined Patent Publication No. Hei 8-288316 (FIG. 1)
[Patent Reference 2] Japanese Unexamined Patent Publication No. 2001-237337 (FIG. 1)
[Patent Reference 3] Japanese Unexamined Patent Publication No. 2002-190488